The present invention relates generally to integrated circuits (ICs), and more particularly, to an IC design verification system.
Integrated circuits (ICs) are verified for correct functionality and logical accuracy to ensure they are free of design related errors. Verification is performed using electronic design verification tools. Many IC designs include multiple functional and logical circuits that are referred to as Intellectual Property (IP) modules or IP cores. The IP cores are inter-connected based on design specifications. Examples of IP cores include serial ports, audio components, generic digital signal processors (DSPs), codec processors, and graphics processing units (GPUs).
The IP cores are verified using verification modules (also known as verification IPs or VIPs). VIPs are standard-compliant and reusable verification blocks that are used in the design verification tools for functional verification of the cores. Examples of VIPs include bus functional models, traffic generators, protocol monitors, and functional coverage blocks. The VIPs are connected to the I/O ports of the IP cores to initiate the verification process.
An IC design is often verified in two stages, IP level verification and SoC level verification. For IP level verification, the design verification apparatus verifies each IP core using a corresponding VIP, and for SoC level verification, it verifies the SoC as a whole, which may include verifying two or more IP cores together using two or more VIPs. Existing SoC level verification methods are tedious and time consuming as they require a considerable amount of time for re-configuring connections between the IP cores and VIPs after the completion of the IP level verification. The number of interconnections increases manifold with the complexity of the IC, which further increases the verification time. Moreover, if an error in connections is identified during SoC level verification, the connections have to be re-configured afresh, which for an IC design with high complexity, may take multiple man weeks. Thus, existing testing tools and techniques introduce a significant delay in time-to-market (TTM) of an integrated circuit.
Therefore, there is a need for a solution that reduces the time required for configuring connections between IP cores of an IC design and corresponding VIPs during SoC level verification, that reduces the time required for verifying an IC design, and that overcomes the above-mentioned limitations of existing design verification solutions.